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IP Cores(CPU) - List of Manufacturers, Suppliers, Companies and Products

Last Updated： Aggregation Period:Jan 07, 2026～Feb 03, 2026
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IP Cores Product List

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TOE100G-IP core for FPGA

TOE100G-IP core for FPGA

Achieving 100G TCP/IP communication functionality with pure hardware logic without CPU!

The 100GbE TCP Offloading Engine IP Core (TOE100G-IP) is a groundbreaking solution that enables the implementation of complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, using only pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

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TOE10G-IP core for FPGA

TOE10G-IP core for FPGA

Achieving 10 times faster 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 10GbE TCP Offloading Engine IP Core (TOE10G-IP) is a groundbreaking solution that allows complex TCP transmission and reception processing, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

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TOE40G-IP core for FPGA

TOE40G-IP core for FPGA

Achieving 40 times speed 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 40GbE TCP Offloading Engine IP Core (TOE40G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

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NVMe IP core for FPGA

NVMe IP core for FPGA

Supports PCIe Gen4 SSD, no external memory required, 2ch RAID0, compatible with random access.

The NVMe IP core is an IP core that interfaces next-generation storage PCIe SSDs, which serve as a replacement for SATA SSDs, with FPGAs without the need for a CPU or external memory. A reference design that operates on various Xilinx/Intel FPGA evaluation boards is included as standard, allowing development to start based on this reference design, enabling rapid product development. This NVMe IP core maximizes the performance of NVMe PCIe SSDs, achieving high-speed transfers of over 3300MB/s (evaluated with KCU105 and Samsung 970 Pro). Time-limited bit/sof files for various Xilinx/Intel FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase.

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25G TOE IP core for FPGA

25G TOE IP core for FPGA

Achieving 25G TCP/IP communication functionality with pure hardware logic without CPU!

The 25GbE TCP Offloading Engine IP Core (TOE25G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time. It provides 25G performance and bandwidth, which is 2.5 times that of the conventional 10G in a single channel. This significantly reduces power consumption and cost per gigabit.

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Sprite Drawing IP Core (Verilog)

Sprite Drawing IP Core (Verilog)

Sprite Drawing IP Core (Verilog)

This process overlays character images (sprites) onto a background image. The maximum image size is 1024x1024. Arbitrary angle rotation in 0.35-degree increments. During rotation, a bi-linear interpolated image is created. Mirror flipping. Alpha blending. The maximum number of overlays is 16.

  • Other semiconductors
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UDP 10G IP Core for FPGA

UDP 10G IP Core for FPGA

Achieving 10Gbps UDP communication functionality with pure hardware logic without CPU!

The 【UDP10G IP Core】 is a groundbreaking solution that allows UDP transmission and reception processing to be implemented solely with pure hardware logic, without the need for a CPU. It also supports high-speed simultaneous transmission and reception. This can help shorten the development time for network application products that require broadcasting and low latency. Additionally, we have prepared demo files for Xilinx/Intel FPGA evaluation boards, allowing you to evaluate and test this core on actual hardware before purchase.

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IP core "AndesCore AX25"

IP core "AndesCore AX25"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Options such as branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection are available. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

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Hardware Master IP

Hardware Master IP

Japan's first! The "Ether CAT Master IP" has been born, significantly reducing software load for high-performance SoC FPGAs.

[ Solving CPU Load and Jitter Issues in EtherCAT MASTER Communication ] To allow more users to use it flexibly, we have developed an IP for SoC FPGA. The communication engine using FPGA hardware achieves high-speed communication intervals and stable communication cycles, reducing software load. <Features> ● Automatic packet generation function ● Process communication (cyclic communication) function: 62.5μs and above ● Automatic retransmission function

  • Embedded Board Computers
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IEEE1588-2008 PTP Time Synchronization IP Core

IEEE1588-2008 PTP Time Synchronization IP Core

Providing IEEE1588-2008 PTP time synchronization solutions as an IP core. Synchronizing devices on Ethernet (LAN) with nanosecond precision.

Oregano Systems offers timing synchronization solutions compliant with IEEE1588-2008 Precision Time Protocol as IP CORE. It provides syn1588 Clock_S for serial connection to external CPUs and syn1588 Clock_M for parallel connection, available in netlist or source code. Synchronization in the nanosecond range over Ethernet is possible. Support for 802.1AS will be available starting summer 2016.

  • syn1588 Clock_M GMII.jpg
  • LAN construction and wiring work
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Digital Simple Radio Transmitter "TFT405DA Model/TFR400DB Model"

Digital Simple Radio Transmitter "TFT405DA Model/TFR400DB Model"

Stable RTK-GNSS surveying is possible! Dustproof and rainproof structure compliant with IP45 for outdoor installation.

The "TFT405DA/TFR400DB" is a digital simple wireless transmitter that achieves an effective communication speed of 9600 bps. It adopts the π/4 shift QPSK modulation method and boasts one of the fastest communication speeds among digital simple wireless devices, specifically designed for data transmission. It is suitable for GPS-equipped surveying instruments, telemetry, and long-distance data transmission, with an interface that outputs and inputs at RS232C levels, making it easy to connect with external devices. 【Features】 - Achieves low power consumption with a general-purpose single-chip CPU configuration through a uniquely developed algorithm. - A license application is required to establish a simple wireless station (no radio operator qualification is necessary). - Suitable for RTK-GPS surveying instruments, telemetry, and long-distance data transmission. - Utilizes a one-touch metal connector for the connection part. - Complies with IP45 for dust and rain resistance, allowing for outdoor installation as is. *For more details, please refer to the PDF document or feel free to contact us.

  • Communications
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SATA IP core for FPGA

SATA IP core for FPGA

High-performance, high-reliability IP core proven by NASA (National Aeronautics and Space Administration).

The Serial ATA (SATA) IP core complies with Serial ATA Revision 3.0 and is designed to operate on FPGA devices such as Xilinx UltraScale, 7 Series, and Intel 10 Series. This IP core provides only the link layer, but reference designs for the transport layer and physical layer are available, allowing connection to SATA3 hard disks without a PHY chip. This SATA IP core maximizes the performance of SSDs, enabling high-speed transfers exceeding 500MB/s per channel. Limited-time evaluation demo files for various FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase. Additionally, the core product comes standard with reference designs that operate on various Xilinx/Intel FPGA evaluation boards, enabling development to start based on this reference design, which allows for rapid product development.

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TOE1G-IP core for FPGA

TOE1G-IP core for FPGA

You can implement TCP/IP communication functionality with pure hardware logic without a CPU!

The TCP Offloading Engine IP Core (TOE1G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Altera FPGAs, which can help shorten product development time.

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IP core "AndesCore S8"

IP core "AndesCore S8"

A secure MPU against memory tampering! It is equipped with a shield against side-channel attacks.

The "AndesCore S8" is an IP core based on the N8 core computing engine, with added features to address security against hacking. The secure memory protection unit (MPU: Memory Protection Unit) at the center strictly protects execution and access according to multiple security levels. Additionally, it includes defenses against hacking targeting the interface between the CPU and memory, as well as the capability to monitor the CPU's power usage signature to prevent program hacking. 【Specifications】 ■ Secure MPU against memory tampering ■ Shield against side-channel attacks ■ Secure debugging for multi-party software development ■ Flexible configuration and runtime control *For more details, please refer to the related links or feel free to contact us.

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IP core "DQ8051CPU"

IP core "DQ8051CPU"

You can easily verify the package at each stage of the SoC design flow!

The "DQ8051CPU" is an IP core for a single-chip 8-bit embedded microcontroller designed to operate with both high-speed (on-chip) and low-speed (off-chip) memory. It is 100% binary compatible with the 8051 8-bit microcontroller and is specifically designed with a focus on performance-to-power consumption ratio, featuring an advanced Power Management Unit (PMU). Additionally, it includes a built-in DoCD-JTAG on-chip debugger and supports the Keil μVision development platform as well as standalone DoCD debugging software. 【Specifications (partial)】 ■ 100% compatibility with 8051 ■ Capable of executing 28.40 times faster than the original 80C51 at the same frequency due to a quad-pipeline architecture ■ Up to 26.721 VAX MIPS at 100MHz ■ 24 times faster multiplication ■ 12 times faster division *For more details, please download the PDF (English version) or feel free to contact us.

  • Other electronic parts
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IP core "AndesCore AX25MP"

IP core "AndesCore AX25MP"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25MP" is a 64-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N9"

IP core "AndesCore N9"

Designers can set specific parameters to adjust the size, power consumption, and performance of the CPU!

The "AndesCore N9" is an IP core designed for applications that require interrupt response capabilities, such as wireless networking, sensors, microcontrollers, and automotive electronics. The low-power N9 family processor has a small gate count, low interrupt latency, and low-cost debugging. The processor family provides excellent performance and outstanding interrupt handling response while addressing the challenges of low dynamic and static power constraints. 【Specifications】 ■ High-performance V3 ISA based on a compact CPU architecture ■ Excellent overall performance ■ Efficient pipeline optimized for local memory access ■ High configurability including AXI bus support *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore A25MP"

IP core "AndesCore A25MP"

Symmetric multi-processor with up to 4 cores! Supports level-2 cache and cache coherence.

The "AndesCore A25MP" is a 32-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to four cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N22"

IP core "AndesCore N22"

There are configurable settings that allow for trade-offs between core size and performance requirements!

The "AndesCore N22" is a 32-bit, dual-stage pipeline CPU IP core based on the AndeStar V5 architecture, designed for embedded applications that require low power consumption and small circuit size. It complies with RISC-V technology and features several efficient performance capabilities, including simple dynamic branch prediction, instruction cache, and local memory. Additionally, it comes with a rich set of optional features such as a JTAG debug interface for development support. 【Specifications (partial)】 ■ AndeStar V5/V5e Instruction Set Architecture (ISA) based on RISC-V technology ■ Supports RV32IMAC/EMAC ■ Andes extensions that enable high performance and high functionality ■ 32-bit, dual-stage pipeline CPU architecture ■ High code density with mixed 16/32-bit instruction formats *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N13"

IP core "AndesCore N13"

With an 8-stage pipeline and a clock frequency exceeding 1GHz, the core delivers excellent performance of 2.05 DMIPS/MHz!

The "AndesCore N13" is a high-performance CPU core designed for compute-intensive applications running on operating systems or bare metal. It is designed to meet the stringent requirements of application processors for consumer electronics such as HDTVs, home media servers, and set-top boxes, as well as the SoCs for switches and routers that deliver content to these devices. Equipped with a memory management unit, L1/L2 cache, local memory, DMA, FPU, vector interrupts, and branch prediction, it can easily run complex operating systems like Linux. 【Specifications】 ■ Optimized pipeline for best performance at 1GHz or higher ■ Dynamic branch prediction accelerates loop execution ■ ULM (Unified Local Memory) for parallel access ■ 64-bit AXI bus for high bandwidth and low latency ■ MMU and MPU for Linux and RTOS ■ Supports FPU coprocessor and L2 cache *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore A25"

IP core "AndesCore A25"

It also includes modes for low power consumption and power management, as well as a debugging interface!

The "AndesCore A25" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extension features that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N25F"

IP core "AndesCore N25F"

High code density 16/32-bit mixed instruction format!

The "AndesCore N25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count, supporting single-precision and double-precision floating-point instructions. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available for separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore D25F"

IP core "AndesCore D25F"

A flexibly configurable platform to support a wide range of system event scenarios!

The "AndesCore D25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. For Linux-based applications, it supports the RISC-V P-extension (draft) DSP/SIMD ISA, which has been significantly contributed to by Andes Technology, as well as single-precision/double-precision floating-point instructions and an MMU. Additionally, options are available for branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore NX25F"

IP core "AndesCore NX25F"

Optimized for high operating frequency and high performance! Supports single-precision/double-precision floating-point instructions.

The "AndesCore NX25F" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Additionally, Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available under separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

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