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IP Cores(CPU) - List of Manufacturers, Suppliers, Companies and Products

Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
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IP Cores Product List

1～15 item / All 24 items

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TOE1G-IP core for FPGA

TOE1G-IP core for FPGA

You can implement TCP/IP communication functionality with pure hardware logic without a CPU!

The TCP Offloading Engine IP Core (TOE1G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Altera FPGAs, which can help shorten product development time.

  • ASIC

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TOE100G-IP core for FPGA

TOE100G-IP core for FPGA

Achieving 100G TCP/IP communication functionality with pure hardware logic without CPU!

The 100GbE TCP Offloading Engine IP Core (TOE100G-IP) is a groundbreaking solution that enables the implementation of complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, using only pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC

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TOE10G-IP core for FPGA

TOE10G-IP core for FPGA

Achieving 10 times faster 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 10GbE TCP Offloading Engine IP Core (TOE10G-IP) is a groundbreaking solution that allows complex TCP transmission and reception processing, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC

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TOE40G-IP core for FPGA

TOE40G-IP core for FPGA

Achieving 40 times speed 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 40GbE TCP Offloading Engine IP Core (TOE40G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC

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NVMe IP core for FPGA

NVMe IP core for FPGA

Supports PCIe Gen4 SSD, no external memory required, 2ch RAID0, compatible with random access.

The NVMe IP core is an IP core that interfaces next-generation storage PCIe SSDs, which serve as a replacement for SATA SSDs, with FPGAs without the need for a CPU or external memory. A reference design that operates on various Xilinx/Intel FPGA evaluation boards is included as standard, allowing development to start based on this reference design, enabling rapid product development. This NVMe IP core maximizes the performance of NVMe PCIe SSDs, achieving high-speed transfers of over 3300MB/s (evaluated with KCU105 and Samsung 970 Pro). Time-limited bit/sof files for various Xilinx/Intel FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase.

  • ASIC

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25G TOE IP core for FPGA

25G TOE IP core for FPGA

Achieving 25G TCP/IP communication functionality with pure hardware logic without CPU!

The 25GbE TCP Offloading Engine IP Core (TOE25G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time. It provides 25G performance and bandwidth, which is 2.5 times that of the conventional 10G in a single channel. This significantly reduces power consumption and cost per gigabit.

  • ASIC

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Sprite Drawing IP Core (Verilog)

Sprite Drawing IP Core (Verilog)

Sprite Drawing IP Core (Verilog)

This process overlays character images (sprites) onto a background image. The maximum image size is 1024x1024. Arbitrary angle rotation in 0.35-degree increments. During rotation, a bi-linear interpolated image is created. Mirror flipping. Alpha blending. The maximum number of overlays is 16.

  • Other semiconductors

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UDP 10G IP Core for FPGA

UDP 10G IP Core for FPGA

Achieving 10Gbps UDP communication functionality with pure hardware logic without CPU!

The 【UDP10G IP Core】 is a groundbreaking solution that allows UDP transmission and reception processing to be implemented solely with pure hardware logic, without the need for a CPU. It also supports high-speed simultaneous transmission and reception. This can help shorten the development time for network application products that require broadcasting and low latency. Additionally, we have prepared demo files for Xilinx/Intel FPGA evaluation boards, allowing you to evaluate and test this core on actual hardware before purchase.

  • ASIC

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SATA IP core for FPGA

SATA IP core for FPGA

High-performance, high-reliability IP core proven by NASA (National Aeronautics and Space Administration).

The Serial ATA (SATA) IP core complies with Serial ATA Revision 3.0 and is designed to operate on FPGA devices such as Xilinx UltraScale, 7 Series, and Intel 10 Series. This IP core provides only the link layer, but reference designs for the transport layer and physical layer are available, allowing connection to SATA3 hard disks without a PHY chip. This SATA IP core maximizes the performance of SSDs, enabling high-speed transfers exceeding 500MB/s per channel. Limited-time evaluation demo files for various FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase. Additionally, the core product comes standard with reference designs that operate on various Xilinx/Intel FPGA evaluation boards, enabling development to start based on this reference design, which allows for rapid product development.

  • ASIC

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IP core "AndesCore S8"

IP core "AndesCore S8"

A secure MPU against memory tampering! It is equipped with a shield against side-channel attacks.

The "AndesCore S8" is an IP core based on the N8 core computing engine, with added features to address security against hacking. The secure memory protection unit (MPU: Memory Protection Unit) at the center strictly protects execution and access according to multiple security levels. Additionally, it includes defenses against hacking targeting the interface between the CPU and memory, as well as the capability to monitor the CPU's power usage signature to prevent program hacking. 【Specifications】 ■ Secure MPU against memory tampering ■ Shield against side-channel attacks ■ Secure debugging for multi-party software development ■ Flexible configuration and runtime control *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore AX25MP"

IP core "AndesCore AX25MP"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25MP" is a 64-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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